SUSHI@NIST: Rolling Next-Generation Secure Hardware into Standards

Enhancing Hardware Security for the Future of National Defense and Emerging Technologies

In an era of geopolitical uncertainty, global semiconductor disruptions, and a rising demand for digital sovereignty, hardware security has become a critical component of national security, economic resilience, and technological leadership.

Secure hardware is essential to the reliability of various modern systems, including advanced defense systems, next-generation AI, and edge computing. However, we now face a new threat landscape characterized by hardware-level vulnerabilities that can bypass conventional protections and compromise entire platforms. These attacks reveal significant weaknesses in today’s computing infrastructure, jeopardizing performance, privacy, national security, and critical infrastructure stability.

To address this challenge, we invite you to this year’s SUSHI Workshop: Sustainable Hardware Security @ NIST. This event will bring together leaders in government, industry, and academia to develop scalable, sustainable, and mission-aligned solutions throughout the semiconductor lifecycle. Key themes will include:

• Threat categorization and mitigation across hardware and firmware layers
• Security and assurance in the semiconductor development lifecycle and supply chains
• Protection strategies for AI-integrated, heterogeneous, and mission-critical systems
• Frameworks for hardware security assurance and scalable adoption
• Embedded and firmware-level resilience

At this year’s workshop, SUSHI will also initiate a national dialogue to create a “Semiconductor Development Life Cycle Security Framework” — a foundational effort to guide the secure design, development, and deployment of trusted microelectronics in critical systems. Outcomes from this workshop will be reflected in a published roadmap and post-workshop report, directly informing national strategy and industry practices.

NIST invites stakeholders to come together and shape the next generation of hardware trust and assurance. Your voice and leadership are essential as we build a collective roadmap for a more secure semiconductor future.

Workshop Organizers:

Jay Rekhi and Yang Guo – National Institute of Standards and Technology (NIST)

Jeyavijayan Rajendran – Texas A&M University, USA

Gang Qu – University of Maryland, USA

Ahmad-Reza Sadeghi – TU Darmstadt, Germany

Confirmed Speakers and Panelists:

Mary Bedner, NIST

Norman Chang, Ansys/Synopsys

Jason Fung, Intel

Blake Gray, Micron

Bernard McShea, DARPA

Jeremy Muldavin, Cadence

Warren Savage, ARLIS

Selcuk Uluagac, NSF

Jim Well,  USAPAE

Greg Yeric, NSTC

Qiaoyan Yu, NSF

William Zortman, Sandia